Various processes and techniques are known for controlling etch or trimming processes to reduce variation in feature profiles on a semiconductor wafer. For example, US 2011/0163420, which is hereby incorporated by reference in its entirety, describes a process of adjusting a photomask pattern by placing a polymer layer over an underlayer on the wafer. The mask is selectively trimmed to generate individual mask. The process involves various deposition and/or etch phases, which include trim steps to form features having an increased aspect ratio. U.S. Pat. No. 7,018,780, which is hereby incorporated by reference in its entirety, describes a technique for removing photoresist material from a semiconductor layer. The method is designed to control and reduce profile variation during photoresist trimming by applying a conformal layer of polymer over the photoresist mask and a portion of the wafer not covered by the mask. The thickness of the conformal layer varies depending on the region of the semiconductor. As a result, during trimming the center-to-edge profile variation of photoresist lines critical dimensions is controlled.
In other known processes, deposition and etching processes achieving a desired critical dimension (CD) target and CD uniformity pattern on the wafer can call for multiple optimization steps in a development cycle. For example, US 2011/0143462, which is hereby incorporated by references in its entirety, discloses a process in which the first optimization cycle can involve tuning the CD target by applying a trim step that controls the CD by varying the step time. After achieving the CD target, the uniformity can be optimized by tuning the electrostatic chuck (ESC) temperature which controls the wafer surface reaction temperature. This process can specify the use of multiple wafers and include the critical parameters being redeveloped every time a different CD target is requested, the incoming CD or CD uniformity changes. If the incoming wafer varies in comparison with the outgoing wafer with regard to an initial CD and CD uniformity, achieving an optimal post CD and CD uniformity target on a wafer by wafer basis is not feasible, as achieving a desired post CD and CD uniformity target uses an iterative process. In known systems, an etch tool designed for a specific lithography tool is used to ensure that any systematic non-uniformity inherent in etch tools could be compensated for by the lithography tool. Use of this tool, however, does not compensate for the non-uniformities resulting from process parameters of the recipe.